'timescale  1ns/1ns

module flow_led_tb(
reg clk;
reg rst_n;
wire [3:0]  led);


initial
     begin
	 clk=1'b1;
	 rst_n=1'b0;
	 #10  rst_n=1'b1;
	 end
	 always#5 clk<=~clk;
	 
	 flow_led_tb
	 #(.cnt_max(25'd24999999)
	 
	 )
	 flow_led_inst(
	 
	 .clk(clk)
	 .rst_n(rst_n)
	 .led(led)
)
endmodule